AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 398

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20.6.12
Name:
Access Type:
Offset:
Reset Value:
• P0-31: Glitch Filter Enable
32072G–11/2011
P31
P23
P15
P7
31
23
15
7
0: Glitch filter is disabled for the corresponding pin.
1: Glitch filter is enabled for the corresponding pin.
NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the
corresponding pin is enabled can cause an unintentional interrupt to be triggered.
Glitch Filter Enable Register
P30
P22
P14
P6
30
22
14
GFER
Read, Write, Set, Clear, Toggle
0xC0, 0xC4, 0xC8, 0xCC
-
6
P29
P21
P13
P5
29
21
13
5
P12
P28
P20
P4
28
20
12
4
P27
P19
P11
P3
27
19
11
3
P26
P18
P10
P2
26
18
10
2
P25
P17
P9
P1
25
17
9
1
P24
P16
P8
P0
24
16
8
0
398