AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 183
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 183 of 1012
- Download datasheet (16Mb)
15.6.4.1
32072G–11/2011
Read waveforms
•NRD waveform
•NCS waveform
access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
Figure 15-7. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time.
NBS0, NBS1,
1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
3. NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
A[AD_MSB:2]
A0, A1
falling edge.
ing edge.
ing edge.
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
D[15:0]
CLK_SMC
NRD
NCS
NCSRDSETUP
NRDSETUP
Figure 15-7 on page
NCSRDPULSE
NRDPULSE
NRDCYCLE
183.
NRDHOLD
NCSRDHOLD
183
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