AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 520

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.8
24.7.9
32072G–11/2011
Loop Mode
Interrupt
Figure 24-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is
connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and
RX_CLOCK is connected to TX_CLOCK.
Most bits in the SR register have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).
These registers enable and disable, respectively, the corresponding interrupt by setting and
clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the genera-
tion of interrupts by asserting the SSC interrupt line connected to the interrupt controller.
Figure 24-16. Interrupt Block Diagram
STTDLY is written to zero.
T ra n s m itte r
R e c e iv e r
T X E M P T Y
R X S Y N C
T X S Y N C
O V R U N
T X R D Y
R X R D Y
RX_DATA
Start = Enable Receiver
DATLEN
To RHR
Data
IE R
S e t
In te rru p t
C o n tro l
IM R
DATLEN
To RHR
Data
C le a r
ID R
S S C In te rru p t
520