AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 187

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.4.3
15.6.4.4
32072G–11/2011
NCS waveforms
Write waveforms
•NWE waveforms
Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS
The write protocol is similar to the read protocol. It is depicted in
write cycle starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined.
1. NWESETUP: the NWE setup time is defined as the setup of address and data before
2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE
3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after
1. NCSWRSETUP: the NCS setup time is defined as the setup time of address before the
2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS
3. NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS
A[AD_MSB:2]
NBS0, NBS1,
the NWE falling edge.
rising edge.
the NWE rising edge.
NCS falling edge.
rising edge;
rising edge.
A0, A1
CLK_SMC
D[15:0]
NRD
NCS
t
PACC
Data Sampling
Figure 15-11 on page
188. The
187