AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 695
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 695 of 1012
- Download datasheet (16Mb)
• SHORTPACKET: Short Packet Interrupt
• STALLEDI: STALLed Interrupt
• CRCERRI: CRC Error Interrupt
• OVERFI: Overflow Interrupt
• NAKINI: NAKed IN Interrupt
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt
• NAKOUTI: NAKed OUT Interrupt
• HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt
• UNDERFI: Underflow Interrupt
32072G–11/2011
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
should be Data0.
For High-bandwidth isochronous endpoint, an EPnINT interrupt is triggered if:
- MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one).
- DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one)
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This bit is set for non-control OUT endpoints, when a short packet has been received.
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and
the Automatic Switch (AUTOSW) bit are written to one.
This triggers an EPnINT interrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing
a one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first
bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N
transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this
case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT
interrupt if HBISOFLUSHE is one.
This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N
bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINERRE is one.
This bit is cleared when the HBISOINERRIC bit is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochronous feature is supported by the device.
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
UNDERFE is one.
695
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