AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 707

• Manufacturer Part Number: AT32UC3A364
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• BUFFCLOSEINEN: Buffer Close Input Enable
• LDNXTCHDESCEN: Load Next Channel Descriptor Enable
• CHEN: Channel Enable
32072G–11/2011
LDNXTCHDES
CEN
For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB
OUT data transfer (received short packet).
For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.
For high-speed OUT isochronous, it may make sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA
transfer is closed when the received PID packet is not MDATA.
Writing a zero to this bit to disable this feature.
1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit
is reset.
0: no channel register is loaded after the end of the channel transfer.
If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN
endpoint, or endpoint is full for OUT endpoint).
Writing this bit to zero will disabled the DMA channel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is
written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both
UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.
Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer. Then any pending request
will start the transfer. This may be used to start or resume any requested transfer.
This bit is cleared when the channel source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by
descriptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.
If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the
UDDMAnSTATUS.CHEN bit is cleared.
If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
0
0
1
1
CHEN
Table 26-6.
0
1
0
1
Current Bank
stop now
Run and stop at end of buffer
Load next descriptor now
Run and link at end of buffer
DMA Channel Control Command Summary
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