RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 78

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.3 Write-Only Control and Status
3-12
Event Counter Mechanism
The event counter mechanism is enabled by setting INT_DELAY
(EN_STAT_CNT) to a logic high. An internal counter is implemented that counts
the number of status queue write events. The number of events before opening the
interrupt window is programmable via the INT_DELAY(STAT_CNT) field. The
window will be closed for STAT_CNT number of events. When the internal
counter has reached the value of STAT_CNT, the interrupt window will be
opened, which will allow the interrupt to propagate to the output pin. The counter
is reset when the status registers are read and the interrupt output goes inactive.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234