RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 241

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
states that the memory controller uses to access the SRAM. A logic zero indicates
zero wait state or single-cycle memory, while a logic one indicates one wait state
or two-cycle memory. The power-on default is MEMCTRL=1, selecting one wait
state or two-cycle memory accesses.
processor follow the convention for SRAM accesses; that is, either zero or one
wait state, depending on MEMCTRL programming. Subsequently, the local
processor sees no functional timing differences between accesses to registers or
SRAM. The internal register accesses from the PCI slave interface are always
zero wait state. When the RS8234 decodes a PCI slave read to its address space,
the RS8234 performs a prefetch of four subsequent (contiguous) word locations.
speed, as well as the amount and organization of the memory. The required
system clock speed for a given application is dependent on the physical line rate,
number of VCCs, and the percentage of idle cells versus assigned cells. Memory
access times and other requirements are specified at three typical
implementations of one, two, and four banks of by_8 SRAM. In terms of address
bus loading, one bank of by_8 SRAM equals one-half bank of by_16 or two
banks of by_4. In this way, the system designer can choose the appropriate SRAM
characteristics to suit the amount of memory and organization required for the
application. See
The MEMCTRL bit in the CONFIG0 Register selects the number of wait
Accesses made to the control registers and internal SRAM by the local
SRAM access time requirements are directly proportional to the system clock
Mindspeed Technologies
Chapter 15.0
for timing information.
™
9.2 Memory Bank Characteristics
9.0 Local Memory Interface
9-5