RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 133

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
5.4.11 Firewall Functions
28234-DSH-001-B
5.4.11.2 Operation
5.4.11.1 Setup
the FIFO. External circuitry must also ensure that only complete cells are written
into the host FIFO.
64-byte aligned.
Implementation of multiple free buffer queues and EPD performs a firewalling
functionality on a group basis.
The firewall mechanism allows the user to allocate buffer credits on a per-channel
basis.
NOTE:
Set RSM_FQCTRL(FBQ0_RTN) to a logic high. This sets free buffer queue
block 0 to contain queues with four word entries. This is used to support per-VCC
firewall credit update.
field (FWALL_EN), to globally enable firewall processing on a per-channel
basis.
for firewall processing:
the entry where credit will initially be returned. Typically, this will be the first
entry after the initial buffers placed on the queue. Write the FWD_VLD bit in all
free buffer queue entries to a logic low.
Whenever a buffer is taken off free buffer queues 0 through 15 during reassembly
on a channel enabled for firewall processing, the RSM coprocessor decrements
the RX_COUNTER[15:0] in the RSM VCC table entry for that channel. This
allows COM buffers to be placed on queues 16 through 31 without being
firewalled.
RSM coprocessor declares a firewall condition. If the firewall condition occurs
on a BOM or SSM, the RS8234 writes a status queue entry with the FW bit set
and a NULL in the BD_PNTR field.
initiates EPD and writes a status queue entry with the FW and EPD bits set. It
then discards cells on that channel until the channel has recovered from the
firewall condition.
The beginning of a cell transfer can be detected by the PCI address being
The user can also set up per-VCC firewalling on a channel-by-channel basis.
Set the global firewall control bit to a logic high in register RSM_CTRL0,
Set the following fields of the VCC Table entry for the channel being set up
• The FW_EN bit set to a logic high enables firewall processing on that
• Set RX_COUNTER[15:0] to assign the initial buffer credit for the
Initialize the FORWARD fields in the free buffer queue base tables to point to
If the RX_COUNTER[15:0] for a channel is 0 when a buffer is required, the
If the firewall condition occurs on a COM or EOM, the RSM coprocessor
When firewalling is enabled in the RSM coprocessor and an FBQ empty
(underflow) condition is encountered, the RX_COUNTER field in the
VCC table(s) still decrements each time the VCC receives a BOM cell.
The RX_COUNTER should not be decremented when the FBQ is empty.
There is no workaround for this problem. The user “must” avoid FBQ
empty conditions when firewalling is enabled.
channel.
channel.
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5.0 Reassembly Coprocessor
5.4 Buffer Management
5-29