RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 263

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
11.2 Unimplemented PCI Bus Interface
Functions
The PCI bus interface on the RS8234 does not implement all the transaction types
defined by the PCI bus specification; only those sections of the protocol that are
necessary for slave and DMA memory accesses are implemented. In particular,
the following transaction types are not implemented:
11.3 PCI Configuration Space
In accordance with the PCI bus specification Revision 2.1, the RS8234 PCI bus
interface implements a 128-byte configuration register space. These
configuration registers can be used by the host processor to initialize, control, and
monitor the SAR bus interface logic. The complete definitions of these registers
and the relevant fields within them is given in the PCI bus specification, and will
not be repeated here. The descriptions and definitions of these register fields as
implemented in the RS8234 is shown in
• 64-bit transfers, as well as the Dual Address Cycle command.
• Snooping and cache support. Memory Read Line, Memory Write and
• Locked and exclusive accesses: the PCI LOCK* line is not driven by the
• I/O accesses (the I/O Read and I/O Write commands).
• Interrupt acknowledge cycles, including the Interrupt Acknowledge
• The Special Cycle command and Special Cycle transactions.
• Burst transfers that do not have simple, sequentially incrementing
Invalidate commands are internally aliased to the Memory Read and
Memory Write commands as per the PCI specification.
RS8234, and the PCI slave interface does not handle locked accesses by
other bus masters in any special manner.
command.
addresses for consecutive data phases. The PCI master logic always
performs sequentially incrementing burst transfers. The two LSBs of the
PCI address lines (AD[1,0]) must be zero during the address phase of any
transfer made to the PCI slave logic (indicating sequentially incrementing
burst addresses). If AD[1,0] is not equal to zero, the slave logic will signal
a type A or B target disconnect after the first data phase, forcing the
external master to perform a single word transfer as per the PCI
specification.
Mindspeed Technologies
11.2 Unimplemented PCI Bus Interface Functions
Chapter
™
13.0.
11.0 PCI Bus Interface
11-3