RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 324

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

14.0 SAR Initialization - Example Tables
14.1 Segmentation Initialization
14.1.1 Segmentation Control Registers
14-2
Table 14-1. Table of Values for Segmentation Control Register Initialization
SEG_CTRL
(Segmentation Control
Register)
SEG_VBASE
(SEG Virtual Channel
Connection Base
Address Register)
SEG_PMBASE
(SEG PM Base Address
Register)
SEG_TXBASE
(Segmentation Transmit
Queue Base Register)
Register
SEG_ENABLE
SEG_RESET
VBR_OFFSET
SEG_GFC
DBL_SLOT
CBR_TUN
ADV_ABR_TMPLT
TX_FIFO_LEN
CLP0_EOM
OAM_STAT_ID
SEG_ST_HALT
SEG_LS_DIS
SEG_HS_DIS
TX_RND
TR_SIZE
SEG_SCHB
SEG_VCCB
SEG_BCKB
SEG_PMB
SEG_TXB
XMIT_INTERVAL
TX_EN
14.1 Segmentation Initialization
Before segmentation is enabled, the host must allocate and initialize all of the
segmentation control registers.
Field
Mindspeed Technologies
Initialized
0x1AD
Value
0x1A5
0x17D
0x219
0x13D
0x10
0x20
0x4
0x0
0x8
0-1
0
0
0
1
1
1
0
0
0
0
1
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-1
Must be set to a logic low until initialization of all
segmentation structures is complete. Set to a logic high
to commence segmentation process.
Use CONFIG0(GLOBAL_RESET) to initialize the SAR.
Schedule slot priority equals general priority.
Disable segmentation GFC processing.
Enable two word schedule slot entries.
Enable CBR traffic scheduling.
Enable per-connection MCR & ICR ABR parameters.
Set Transmit FIFO depth to four cells.
Disable CLP on EOM processing.
OAM global status queue set to 16.
Disable status queue entry for a VCC halted with a
partially segmented buffer.
Enable local status queue full check.
Enable host status queue full check.
Round robin transmit queue processing selected.
Transmit queue size set to 64 entries.
Schedule table starts at 0xD280 in SAR shared memory.
SEG VCC table starts at 0xBE80 in SAR shared memory.
VBR bucket table starts at 0x10C80 in SAR shared
memory.
PM table starts at 0xD680 in SAR shared memory.
Transmit queues start at 0x9E80 in SAR shared memory.
Transmit queue update interval set to 32.
Transmit queues 0 through 8 are enabled.
™
lists the initial value(s) for each field.
Notes
28234-DSH-001-B
RS8234