RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 77

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
3.3.2.4 Status Queue
3.3.2.3 Overflow
Interrupt Delay
Conditions
An overflow condition occurs when the SAR attempts to write a status queue
entry, but the status queue entry is unavailable. This condition may happen for
both the segmentation and reassembly status queues. Chapter 4.0, Segmentation
Coprocessor, and Chapter 5.0, Reassembly Coprocessor, describe the handling of
this event. In either case, the result is severe and therefore undesirable. The host
control service rate of the status queue should match or exceed the status queue
reporting rate of the RS8234.
pointer to the READ_UD pointer, i.e., the last known host READ position. If
WRITE points to the entry immediately before the READ_UD (WRITE =
READ_UD -1), the SAR detects the imminent overflow condition.
(OVFL) in the exhausted status queue. Since it cannot report status, the RS8234
segmentation and reassembly processing is temporarily halted for VCCs assigned
to the overflowed status queue only. All other processes and queues remain
operational.
Status Queue Interrupt Delay has been added in order to reduce the interrupt
processing load on the host. This is valuable in a Network Interface Card
(NIC)-based solution, where the SAR resides in an environment in which the host
is not dedicated to datacom processing. Both a timer holdoff mechanism and an
event counter mechanism are implemented and work in parallel. The timer
holdoff mechanism uses the ALARM1 and CLOCK register resources to
implement an interval timer. Interrupts due to status queue writes, either host or
local, are delayed until the timer expires. The event counter mechanism delays the
assertion of the interrupt due to status queue writes until a fixed number of status
queue writes have occurred. Both mechanisms work in parallel (not in series) if
enabled, so that either mechanism needs to expire before the interrupt propagates
to the output pin. Interrupts due to conditions other than status queue writes are
not delayed. (See page 13-7 for specific information on the Interrupt Delay
(INT_DELAY) register.)
Timer Holdoff Mechanism
The timer holdoff mechanism is enabled by setting INT_DELAY (EN_TIMER)
to a logic high. The ALARM1 register is set to a value that will hold off the
interrupt for a specified period of time. The user initializes the CLOCK register
to zero. When the value in the CLOCK register is greater than the value in the
ALARM1 register, status queue interrupts will be allowed to propagate to the
appropriate interrupt pins, HINT* or PINT*. The CLOCK register is set to zero
once an interrupt has propagated to the output pin, thus closing the status queue
write interrupt window. The timer mechanism cannot be used in both the PINT*
and HINT* circuits at the same time. The timer mechanism is configured via the
INT_DELAY (TIMER_LOC) bit.
The RS8234 detects an overflow condition by comparing its current WRITE
To inform the host of the event, the SAR sets the overflow indication bit
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3.3 Write-Only Control and Status
3.0 Host Interface
3-11