RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 371

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RS8234EBGC

Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet

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RS8234
ATM ServiceSAR Plus with xBR Traffic Management
A.1 Instruction Register
The Instruction Register is a 4-bit register with no parity. When the boundary scan circuitry is reset, the IR is
loaded with the binary value b1111, which is equivalent to the BYPASS Instruction value. The Capture-IR
binary value is b0001, and is shifted out TDO as the IR is loaded.
SAMPLE/PRELOAD) and thirteen private instructions for manufacturing use only. Bit-0 (LSB) is shifted into
the instruction register first.
NOTE:
Table A-3. IEEE Std. 1149.1 Instructions
28234-DSH-001-B
The 16 instructions include three IEEE 1149.1 mandatory public instructions (BYPASS, EXTEST, and
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
The implementation of this register as described here is applicable only to Rev C of the RS8234 device.
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
Table A-3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
shows the bit settings for this register.
Mindspeed Technologies
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EXTEST
RSTHIGH - Private
SAMPLE/PRELOAD
TMWAFIFO - Private
TMWBFIFO - Private
TMRFIFO - Private
TSEGFIFO - Private
TRSMFIFO - Private
T38AFIFO - Private
T38VBFIFO - Private
RSVD0 - Private
RSVD1 - Private
RSVD2 - Private
RSVD3 - Private
PM_EN - Private
BYPASS
Instruction
Appendix A Boundary Scan
Register Accessed
Boundary Scan
Boundary Scan
Boundary Scan
Boundary Scan
A.1 Instruction Register
A-3

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