RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 310
RS8234EBGC
Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234EBGC.pdf
(401 pages)
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13.0 RS8234 Registers
13.6 Counters and Status Registers
This register contains the interrupt enables that correspond to the status in the HOST_ISTAT1 register. The
assertion of the HRST* system reset pin will clear all of the HOST_IMASK1 interrupt enables.
13-28
0x1d4 - Host Interrupt Mask Register 1 (HOST_IMASK1)
30-27
23-16
9-3
Bit
31
26
25
24
15
14
13
12
11
10
2
1
0
Field
Size
1
4
1
1
1
8
1
1
1
1
1
1
7
1
1
1
EN_PCI_BUS_ERROR
Reserved
EN_DMA_AFULL
EN_FR_PAR_ERR
EN_FR_SYNC_ERR
Reserved
EN_RSQUEUE_FULL
EN_RSM_OVFL
EN_RSM_HS_FULL
EN_RSM_LS_FULL
EN_RSM_HF_EMPT
EN_RSM_LF_EMPT
Reserved
EN_SEG_UNFL
EN_SEG_HS_FULL
EN_SEG_LS_FULL
Name
Mindspeed Technologies
Enables interrupt when PCI_BUS_ERROR status is a logic 1.
Set to zero.
Enabled interrupt when DMA_AFULL status is a logic 1.
Enables interrupt when FR_PAR_ERR status is a logic 1.
Enables interrupt when FR_SYNC_ERR status is a logic 1.
Set to zero.
Enables interrupt when RSQUEUE_FULL status is a logic 1.
Enables interrupt when RSM_OVFL status is a logic 1.
Enables interrupt when RSM_HS_FULL status is a logic high.
Enables interrupt when RSM_LS_FULL status is a logic high.
Enables interrupt when RSM_HF_EMPT status is a logic high.
Enables interrupt when RSM_LF_EMPT status is a logic high.
Set to zero.
Enables interrupt when SEG_UNFL status is a logic high.
Enables interrupt when SEG_HS_FULL status is a logic high.
Enables interrupt when SEG_LS_FULL status is a logic high.
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
28234-DSH-001-B
RS8234
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