RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 236

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

8.0 DMA Coprocessor
8.5 Control Word Transfers
Figure 8-4. Big Endian Misaligned Transfer
8-4
Length (# of 32 bit words) = 3
Host Address = 01
from RSM block
11
3
7
Bytes
0
4
8
1
5
9
10
2
6
0x00
0x04
0x08
0x0C
implied that the data is not aligned.
would map into the PCI host address space for a big endian system.
8.5 Control Word Transfers
If a host system sends control words to the SAR in little endian format, the
reassembly and segmentation blocks must have the capability of byte swapping, to
format these control words to or from big endian.
Swap, MSTR_CTRL_SWAP) and 29 (Slave Control Byte Swap, SLAVE_
SWAP), located in the Special Status Register of the PCI Configuration Space
(address 0x40).
slave write or read access. When MSTR_CTRL_SWAP is a logic high, the
control structures that the SAR writes are written with bytes swapped.
Address
When the RS8234 specifies a host address with the LSBs not equal to 00, it is
Control word byte swapping is controlled by bits 30 (Master Control Byte
When SLAVE_SWAP is a logic high, the slave interface swaps the bytes of a
An active HRST* will cause these bits to be a logic low.
ATM Cell
Mindspeed Technologies
PCI Host Address Space
Host Address = 10
from RSM block
10
2
6
11
0
3
7
Bytes
1
4
0
8
2
5
9
1
3
0x00
0x04
0x08
0x0C
ATM ServiceSAR Plus with xBR Traffic Management
4
5
Address
Figure 8-4
6
™
7
8
Host Address = 11
from RSM block
shows how an unaligned address
5
1
9
9
10
10
Bytes
2
6
11
11
3
7
4
8
0
0x00
0x04
0x08
0x0C
28234-DSH-001-B
Address
RS8234
100074_066