RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 295

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
0xa8 - Schedule Size Register (SCH_SIZE)
The SCH_SIZE register sets the size of the schedule table in schedule slots and the period of a schedule slot in
system clocks.
0xac - Scheduler Control Register (SCH_CTRL)
The SCH_CTRL register defines the configured schedule slot and priority and VBR offsets, when 16 priority
queues are used.
28234-DSH-001-B
31-16
15-14
31-27
25-15
14-12
11-10
13-0
9-6
Bit
Bit
Bit
26
8
7
6
5
4
3
2
1
0
Field
Field
Field
Size
Size
Size
16
14
11
1
1
1
1
1
1
1
1
1
2
5
1
3
2
4
Reserved
TUN_ENA_10
GFC10
Reserved
TUN_ENA_9
GFC9
Reserved
TUN_ENA_8
GFC8
TBL_SIZE[15:0]
Reserved
SLOT_PER[13:0]
Reserved
Reserved
Reserved
SLOT_DEPTH
Reserved
TUN_PRI0_OFFSET
Name
Name
Name
Mindspeed Technologies
NOTE:
Program and read as zero.
Enable tunnel on global priority pointer 10.
Enable GFC on global priority pointer 10.
Program and read as zero.
Enable tunnel on global priority pointer 9.
Enable GFC on global priority pointer 9.
Program and read as zero.
Enable tunnel on global priority pointer 8.
Enable GFC on global priority pointer 8.
Size of schedule table in schedule slots.
Program and read as zero.
Number of system clocks per schedule slot. The value written to the
register should be (SLOT_PER - 1). Minimum bound for SLOT_PER
value = 70.
Program and read as zero.
Program and read as zero.
Depth of the schedule slot is set to 1 + SLOT_DEPTH words. Active only if
USE_SCH_CTRL is asserted.
Program and read as zero.
Offset from the TUN_PRI_0 field in the schedule table and CBR VCC table.
Active only if USE_SCH_CTRL is asserted.
Must be set to 0 during initialization unless using an external
scheduler clock.
™
Description
Description
Description
13.0 RS8234 Registers
13.4 Scheduler Registers
13-13