ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 99
ZL50110GAG
Manufacturer Part Number
ZL50110GAG
Description
CESoP Processor 552-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.ZL50110GAG.pdf
(113 pages)
Specifications of ZL50110GAG
Package
552BGA
Maximum Data Rate
1000 Mbps
Transmission Media Type
Fiber Optic
Power Supply Type
Analog
Typical Supply Current
950(Max) mA
Typical Operating Supply Voltage
1.8 V
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
1.95 V
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ZL50110GAG2
Manufacturer:
ZARLINK
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CPU_DATA[31:0]
CPU_DATA[31:0]
CPU_SDACK2
CPU_TS_ALE
CPU_DREQ1
CPU_SDACK1
CPU_TS_ALE
CPU_DREQ0
CPU_CLK
CPU_WE
CPU_OE
CPU_CS
CPU_TA
CPU_CLK
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted.
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with positive polarity
CPU_WE
CPU_OE
CPU_CS
CPU_TA
CPU_SDACK1 shown with negative polarity
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
t
CWV
t
CWV
Figure 46 - CPU DMA Write - MPC8260
Figure 45 - CPU DMA Read - MPC8260
ZL50110/11/12/14
Zarlink Semiconductor Inc.
t
SDV
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t
CSS
CTS
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CSS
CTS
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CTH
CC
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CKS
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99
CC
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CKS
t
CES
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CTH
t
CPU_CS and CPU_OE must BOTH be asserted to enable
ODV
t
OTV
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t
CES
OTV
t
CKH
t
CKH
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t
CWV
CTV
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t
CDV
CTV
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CWV
t
CDS
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CTV
t
CDH
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CTV
t
CEH
0 or more cycles
0 or more cycles
0 or more cycles
0 or more cycles
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CSH
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CEH
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ODV
SDV
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CSH
Data Sheet
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OTV
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OTV
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