ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 98

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

CPU_ADDR[23:2]
CPU_DATA[31:0]
CPU_ADDR[23:2]
CPU_TS_ALE
CPU_DATA[31:0]
CPU_TS_ALE
CPU_CLK
CPU_WE
CPU_CS
CPU_OE
CPU_TA
CPU_CLK
CPU_WE
CPU_OE
CPU_CS
CPU_TA
NOTE 1: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS
and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3: The CPU_TA maximum assertion time is 4 μs.
NOTE 1: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS
until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is
finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3:The CPU_TA maximum assertion time is 4 μs.
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CAS
CSS
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CAS
CSS
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SDV
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CTS
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CTS
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Figure 44 - CPU Write - MPC8260
Figure 43 - CPU Read - MPC8260
CAH
CTH
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CAH
CTH
ZL50110/11/12/14
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Zarlink Semiconductor Inc.
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ODV
CES
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CES
98
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0 or more cycles
0 or more cycles
CC
CDV
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CC
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CDS
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CTV
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CDH
CEH
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0 or more cycles
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CSH
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0 or
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CEH
CSH
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ODV
SDV
Data Sheet
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