ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 39
![no-image](/images/manufacturer_photos/0/7/726/zarlink_sml.jpg)
ZL50110GAG
Manufacturer Part Number
ZL50110GAG
Description
CESoP Processor 552-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.ZL50110GAG.pdf
(113 pages)
Specifications of ZL50110GAG
Package
552BGA
Maximum Data Rate
1000 Mbps
Transmission Media Type
Fiber Optic
Power Supply Type
Analog
Typical Supply Current
950(Max) mA
Typical Operating Supply Voltage
1.8 V
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
1.95 V
Available stocks
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Part Number:
ZL50110GAG2
Manufacturer:
ZARLINK
Quantity:
60
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M1_RXD[7:0]
M1_RXDV /
M1_RXD[8]
M1_RXER /
M1_RXD[9]
M1_CRS /
M1_Signal_Detect
M1_TXCLK
M1_TXD[7:0]
M1_TXEN /
M1_TXD[8]
Signal
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
I/O
I U
I D
I D
I D
I U
O
O
[7]
[6]
[5]
[4]
M26
L21
L23
L22
[7]
[6]
[5]
[4]
P23
M25
P26
M24
R24
P22
T23
P25
R23
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
MII Port 1
39
N25
N24
R26
T26
R22
P21
T22
R21
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_RXCLK (GMII/MII) or the rising
edges of M1_RBC0 and M1_RBC1 (TBI).
GMII/MII - M1_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
TBI - M1_RXD[8]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
GMII/MII - M1_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M1_RXD[9]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
GMII/MII - M1_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M1_Signal Detect
Similar function to M1_CRS.
MII only - Transmit Clock
Accepts the following frequencies:
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_TXCLK (MII) or the rising edge
of M1_GTXCLK (GMII/TBI).
GMII/MII - M1_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M1_TXD[8]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
25.0 MHz
MII
Description
100 Mbps
Data Sheet
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