ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 97

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

11.8
Note 1:
Note 2:
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of
CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
The CPU_TA maximum assertion time is 4 μs.
CPU_CLK Period
CPU_CLK High Time
CPU_CLK Low Time
CPU_CLK Rise Time
CPU_CLK Fall Time
CPU_ADDR[23:2] Setup Time
CPU_ADDR[23:2] Hold Time
CPU_DATA[31:0] Setup Time
CPU_DATA[31:0] Hold Time
CPU_CS Setup Time
CPU_CS Hold Time
CPU_WE/CPU_OE Setup Time
CPU_WE/CPU_OE Hold Time
CPU_TS_ALE Setup Time
CPU_TS_ALE Hold Time
CPU_SDACK1/CPU_SDACK2
Setup Time
CPU_SDACK1/CPU_SDACK2
Hold Time
CPU_TA Output Valid Delay
CPU_DREQ0/CPU_DREQ1
Output Valid Delay
CPU_IREQ0/CPU_IREQ1 Output
Valid Delay
CPU_DATA[31:0] Output Valid
Delay
CPU_CS to Output Data Valid
CPU_OE to Output Data Valid
CPU_CLK(falling) to CPU_TA
Valid
CPU Interface Timing
Load = 50 pF maximum
The maximum value of t
how to accommodate this during board design.
Parameter
CTV
may cause setup violations if directly connected to the MPC8260. See Section 13.2 for details of
Table 42 - CPU Timing Specification
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CWV
CCH
CCR
CDH
ODV
t
CCL
CCF
CAS
CAH
CDS
CSS
CSH
CES
CEH
CTS
CTH
CKS
CKH
CTV
CRV
CDV
SDV
OTV
CC
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Min.
3.2
3.3
3.2
6
6
4
2
4
2
4
2
5
2
4
2
2
2
2
2
2
2
97
15.152
Typ.
Max.
11.3
10.4
10.4
9.5
4
4
6
6
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1, 2
Note 1
Note 1
Note 1
Data Sheet
Notes