ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 44
ZL50110GAG
Manufacturer Part Number
ZL50110GAG
Description
CESoP Processor 552-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.ZL50110GAG.pdf
(113 pages)
Specifications of ZL50110GAG
Package
552BGA
Maximum Data Rate
1000 Mbps
Transmission Media Type
Fiber Optic
Power Supply Type
Analog
Typical Supply Current
950(Max) mA
Typical Operating Supply Voltage
1.8 V
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
1.95 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ZL50110GAG2
Manufacturer:
ZARLINK
Quantity:
60
- Current page: 44 of 113
- Download datasheet (2Mb)
RAM_ADDR[19:0]
RAM_BW_A#
RAM_BW_B#
RAM_BW_C#
RAM_BW_D#
RAM_BW_E#
RAM_BW_F#
RAM_BW_G#
RAM_BW_H#
RAM_RW#
Signal
Table 14 - External Memory Interface Package Ball Definition (continued)
I/O
O
O
O
O
O
O
O
O
O
O
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
U2
T3
U3
V2
W1
V3
W2
Y1
U4
T2
T1
P5
R3
R2
P4
R1
P2
R4
P3
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
44
P1
N4
N3
N2
M1
M2
M4
M3
M6
M5
Buffer memory address output.
Synchronous to rising edge of
SYSTEM_CLK.
Synchronous Byte Write Enable A (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[7:0].
Synchronous Byte Write Enable B (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[15:8].
Synchronous Byte Write Enable C (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[23:16].
Synchronous Byte Write Enable D (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[31:24].
Synchronous Byte Write Enable E (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[39:32].
Synchronous Byte Write Enable F (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[47:40].
Synchronous Byte Write Enable G (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[55:48].
Synchronous Byte Write Enable H (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[63:56].
Read/Write Enable output
Read = high
Write = low
Description
Data Sheet
Related parts for ZL50110GAG
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
128, 256 and 1024 Channel CESoP Processors
Manufacturer:
ZARLINK [Zarlink Semiconductor Inc]
Datasheet:
Part Number:
Description:
Zarlink Semiconductor Inc [TV IF PREAMPLIFIER]
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
256 x 256 Channels (8 TDM Streams @ 2.048Mb/s) Non-blocking Digital Switch (DX)
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Video Programme Delivery Control Interface Circuit
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
SP8719520MHz LOW CURRENT TWO-MODULUS DIVIDERS
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
REMOTE CONTROL RECEIVER
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
2·5GHz ÷8192 PRESCALER
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
1·3GHz 4256 PRESCALER WITH LOW CURRENT AND LOW RADIATION
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet:
Part Number:
Description:
Manufacturer:
Zarlink Semiconductor
Datasheet: