ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 61

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

5.3.3
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL50110/11/12/14 is capable of providing the TDM clock for either of the modes. The
ZL50110/11/12/14 supports clock recovery in both synchronous and asynchronous modes of operation. In
asynchronous operation each stream may have independent clock recovery.
5.3.3.1
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/12/14 is
acting as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary
and secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to
the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the
output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse
required to drive the TDM streams. See “DPLL Specification” on page 75 for further details.
When the ZL50110/11/12/14 is acting as a slave device, the common clock and frame pulse signals are taken from
an external device providing the TDM master function.
5.3.3.2
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the
internal clock. It is then forwarded to the payload assembly process. The ZL50110/11/12/14 Payload Assembler can
handle up to 128 active packet streams or “contexts” simultaneously. Packet payloads are assembled in the format
shown in Figure 15 - on page 62. This meets the requirements of the IETF CESoPSN standard (RFC 5086).
Alternatively, packet payloads are assembled in the format shown in Figure 17 - on page 64. This meets the
requirements of the IETF SAToP standard (RFC 4553).
The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header
combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context),
which must not exceed 56 bytes.
Payload Assembly
TDM Clock Structure
TDM_CLKi[31:0]
Synchronous TDM Clock Generation
Asynchronous TDM Clock Generation
TDM_CLKiP
TDM_CLKiS
Figure 14 - Synchronous TDM Clock Generation
PRS
SRS
ZL50110/11/12/14
Zarlink Semiconductor Inc.
61
PRD
SRD
DIV
DIV
Internal
DPLL
CLOCK
FRAME
PLL_PRI
PLL_SE
C
Data Sheet