ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 48
ZL50110GAG
Manufacturer Part Number
ZL50110GAG
Description
CESoP Processor 552-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.ZL50110GAG.pdf
(113 pages)
Specifications of ZL50110GAG
Package
552BGA
Maximum Data Rate
1000 Mbps
Transmission Media Type
Fiber Optic
Power Supply Type
Analog
Typical Supply Current
950(Max) mA
Typical Operating Supply Voltage
1.8 V
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
1.95 V
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3.6
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock. No chip access should occur at this time.
SYSTEM_CLK
SYSTEM_RST
SYSTEM_DEBUG
System Function Interface
Signal
Table 16 - System Function Interface Package Ball Definition
I/O
I
I
I
U6
V4
U5
ZL50110/11/12/14
Package Balls
Zarlink Semiconductor Inc.
48
System Clock Input. The system clock
frequency is 100 MHz. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the
ZL50110/11/12/14 to be reset to their
default state. Recommend external
pull-up.
System Debug Enable. This is an
asynchronous signal that, when
de-asserted, prevents the software
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Description
Data Sheet
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