ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 75

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

8.0
The ZL50110/11/12/14 family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 4/4E
requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the
ZL50110/11/12/14 device operating as a master the DPLL is used to provide clock and frame reference signals to
the internal and external TDM infrastructure. In structured mode, with the ZL50110/11/12/14 device operating as a
slave, the DPLL is not used. All TDM clock generation is performed externally and the input streams are
synchronised to the system clock by the TDM interface. The DPLL is not required in unstructured mode (hence it is
not available) because the TDM clocks and frame signals are generated by internal DCO’s assigned to each
individual stream.
8.1
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown
mode.
8.1.1
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event
of a failure. These references should have the same nominal frequencies but do not need to be identical as long as
their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the
available TDM input stream clocks (up to 32 on the ZL50111 variant), or from the external TDM_CLKiP (primary) or
TDM_CLKiS (secondary) input pins, as illustrated in Figure 14 - on page 61. It is possible to supply a range of input
frequencies as the DPLL reference source, depicted in Table 29. The PRD register Value is the number (in
hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency
at PLL_PRI or PLL_SEC.
Note 1:
Note 2:
Note 3:
Input Frequency
44.736 (Note 3)
Modes of Operation
DPLL Specification
Source
16.384
22.368
34.368
(MHz)
A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL.
UI means Unit Interval - in this case periods of the time signal. So ±1UI on a 64 kHz signal means ±15.625 µs, the period of
the reference frequency. Similarly ±1023UI on a 4.096 MHz signal means ±250 µs.
This input frequency is supported with the use of an external divide by 2.
0.008
1.544
2.048
4.096
8.192
6.312
Locking Mode (normal operation)
Tolerance
(±ppm)
130
30
50
50
50
50
30
20
20
20
Table 29 - DPLL Input Reference Frequencies
Divider
Ratio
2796
ZL50110/11/12/14
537
699
1
1
1
1
1
1
1
Zarlink Semiconductor Inc.
75
PRD/SRD
Register
(Note 1)
Value
(Hex)
AEC
2BB
219
1
1
1
1
1
1
1
Frequency at
PLL_PRI or
PLL_SEC
16.384
(MHz)
0.008
1.544
2.048
4.096
8.192
6.312
0.008
0.064
0.064
±1 (on 64k Hz)
±1 (on 64 kHz)
±1 (on 64 kHz)
Input Wander
Acceptable
Maximum
tolerance
(Note 2)
±1023
±1023
±1023
±1023
±1023
±1023
Data Sheet
(UI)
±1