ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 17

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner.
AA
AC
AD
AF
AB
AE
W
L
M
G
J
C
D
H
N
R
U
A
B
E
K
P
V
Y
F
T
PLL_SEC RAM_BW
RAM_BW
RAM_BW
TDM_FR
TDM_CL
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_PA
RAM_PA
RAM_AD
RAM_AD
RAM_AD
RAM_AD
PLL_PRI RAM_BW
GPIO[12] GPIO[13] RAM_DA
RAM_DA
RAM_DA
Mo_REF
RITY[1]
RITY[7]
GPIO[1] GPIO[7]
GPIO[5] GPIO[11] GPIO[14] RAM_DA
DR[12]
DR[17]
TA[10]
TA[15]
TA[21]
TA[25]
TA[29]
DR[5]
DR[9]
TA[34]
TA[35]
GND
TA[3]
GND
GND
KiP
_E
_H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_STo
TDM_STo
RAM_BW
TDM_FR
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_PA
RAM_PA
RAM_AD
RAM_AD
RAM_AD
RAM_AD
RAM_AD
RAM_DA
RAM_DA
RAM_DA
Mi_REF
GPIO[4]
RITY[0]
RITY[6]
TA[13]
TA[18]
TA[24]
TA[28]
DR[10]
DR[14]
DR[18]
TA[36]
TA[40]
TA[50]
DR[4]
DR[6]
TA[1]
TA[9]
[1]
[0]
_A
_D
_G
TDM_STi[
RAM_BW
RAM_BW
RAM_BW
TDM_CL
TDM_CL
TDM_CL
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_PA
RAM_AD
RAM_AD
RAM_AD
RAM_AD
RAM_DA
RAM_DA
RAM_DA
GPIO[0]
GPIO[6] GPIO[10] RAM_DA
GPIO[8] GPIO[15] RAM_DA
Ki_REF
RITY[5]
TA[12]
TA[16]
TA[23]
TA[27]
TA[31]
DR[11]
DR[15]
TA[37]
TA[41]
TA[48]
TA[55]
DR[2]
DR[7]
Ko[3]
TA[5]
KiS
_B
_C
_F
2]
TDM_STo
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_AD
RAM_AD
RAM_AD
RAM_AD
RAM_RW SYSTEM
RAM_DA
RAM_DA
RAM_DA
RAM_DA
TDM_CL
TDM_CL
RAM_PA
SYSTEM
IC_GND
GPIO[3]
RITY[4]
DR[13]
DR[19]
TA[14]
TA[19]
TA[26]
TA[30]
TA[38]
TA[42]
TA[47]
TA[54]
TA[56]
Ko[1]
DR[3]
DR[8]
_RST
Ki[3]
TA[0]
TA[4]
TA[6]
[4]
TDM_STo
TDM_STi[
TDM_STi[
TDM_STi[
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_AD
RAM_AD
_DEBUG
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_DA
RAM_PA
IC_GND
RITY[3]
GPIO[2] VDD_CO
GPIO[9] RAM_DA
DR[16]
TA[11]
TA[17]
TA[22]
TA[32]
TA[39]
TA[43]
TA[46]
TA[53]
TA[57]
TA[61]
TA[2]
TA[7]
DR[0]
GND
GND
GND
[5]
4]
3]
0]
TDM_STi[
TDM_CL
TDM_CL
TDM_CL
TDM_CL
RAM_DA
VDD_CO
RAM_DA
VDD_CO
RAM_PA
RAM_AD
VDD_CO
SYSTEM
VDD_CO
RAM_DA
RAM_DA
RAM_DA
RAM_DA
Ko_REF
TEST_M
RITY[2]
A1VDD
ODE[2]
TA[20]
TA[33]
TA[44]
TA[49]
TA[58]
TA[62]
Ko[6]
Ko[2]
GND
TA[8]
DR[1]
GND
_CLK
GND
Ki[1]
RE
RE
RE
RE
RE
6]
IC
TDM_STo
TDM_STo
TDM_STo
JTAG_TR
JTAG_TDI IC_GND CPU_AD
TDM_CL
TDM_CL
VDD_CO
RAM_DA
RAM_DA
RAM_DA
RAM_DA
TA[45]
TA[51]
TA[59]
TA[63]
Ki[6]
Ki[0]
Figure 4 - ZL50110 Package View and Ball Positions
[7]
[6]
[3]
RE
ST
TDM_STi[
TDM_STi[
TDM_STo
JTAG_TC
TDM_CL
TDM_CL
RAM_DA
RAM_DA
TEST_M
IC_GND CPU_AD
ODE[0]
TA[52]
TA[60]
Ko[4]
N/C
Ki[7]
[2]
7]
5]
K
TDM_STi[
VDD_CO
JTAG_TD
TDM_CL
TDM_CL
TEST_M
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
IC_GND CPU_AD
ODE[1]
DR[3]
DR[5]
Ki[5]
Ko[0]
N/C
N/C
N/C
RE
1]
O
JTAG_TM
TDM_CL
TDM_CL
TDM_CL
CPU_AD
CPU_AD
CPU_AD
DR[10]
Ko[7]
DR[4]
DR[7]
DR[8]
Ki[4]
Ki[2]
GND
N/C
N/C
N/C
S
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
TDM_CL
ZL50110/11/12/14
DR[11]
DR[13]
DR[15]
Ko[5]
GND
GND
GND
GND
GND
GND
DR[2]
DR[6]
DR[9]
N/C
N/C
N/C
N/C
N/C
Zarlink Semiconductor Inc.
VDD_CO
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
CPU_AD
DR[12]
DR[14]
DR[16]
DR[17]
DR[18]
DR[19]
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
RE
VDD_CO
CPU_AD
CPU_AD
CPU_AD
CPU_AD
DR[23]
DR[22]
DR[21]
DR[20]
GND
GND
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
RE
CPU_CLK CPU_DR
VDD_CO
CPU_WE CPU_SD
CPU_TA CPU_DAT
CPU_OE CPU_TS_
CPU_CS CPU_SD
17
GND
GND
GND
GND
GND
GND
N/C
N/C
N/C
N/C
N/C
N/C
RE
CPU_DAT
VDD_CO
ACK2
ACK1
GND
GND
GND
GND
GND
GND
EQ0
N/C
N/C
N/C
N/C
N/C
A[8]
A[1]
ALE
RE
CPU_DAT
CPU_DAT
IC_VDD_I
CPU_IRE
CPU_DR
GND
GND
GND
GND
GND
GND
A[15]
EQ1
N/C
N/C
N/C
N/C
N/C
N/C
A[7]
Q1
IC
O
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_IRE
A[23]
A[12]
A[10]
N/C
N/C
N/C
N/C
N/C
N/C
A[3]
Q0
IC
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
VDD_CO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
A[22]
A[16]
A[6]
A[4]
A[0]
N/C
N/C
N/C
N/C
N/C
N/C
RE
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
A[30]
A[21]
A[14]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
A[9]
A[5]
CPU_DAT
CPU_DAT
CPU_DAT
CPU_DAT
VDD_CO
A[27]
A[20]
A[13]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
A[2]
RE
M1_GTX_
M0_GTX_
CPU_DAT
CPU_DAT
CPU_DAT
VDD_CO
VDD_CO
VDD_CO
M1_TXD[
M1_TXD[
VDD_CO
M0_TXD[
M0_TXD[
VDD_CO
M1_RXE
A[24]
A[18]
A[11]
GND
CLK
CLK
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RE
RE
RE
RE
RE
2]
0]
7]
2]
R
M0_GIGA
M1_TXCL
M0_RXD[
M0_TXERM0_TXEN M0_RXD[
M0_RXCL
CPU_DAT
CPU_DAT
CPU_DAT
BIT_LED
M1_TXD[
M1_TXD[
M1_TXD[
M0_TXD[
M0_TXD[
M0_TXD[
M1_REF
GND
GND
GND
A[29]
A[25]
A[17]
CLK
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
6]
3]
1]
2]
5]
1]
0]
K
K
M1_RXCL
M1_TXER M1_RXD[
M1_TXEN
M0_RXD[
CPU_DAT
CPU_DAT
M1_LINK
M1_CRS
M1_TXD[
M1_TXD[
M0_TXD[
M0_TXD[
M0_TXD[
UP_LED
M_MDC
A[28]
A[19]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
K
5]
4]
5]
6]
4]
3]
M0_RBC0 M0_COL M0_RXD[
CPU_DAT
M1_RXD[
M1_TXD[
M0_TXCL
M0_RXD[
M0_LINK
UP_LED
M0_REF
GND
GND
A[26]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CLK
N/C
N/C
N/C
N/C
5]
2]
7]
K
4]
6]
M1_RBC1 M1_RXD[
M0_RBC1 M0_RXD[
CPU_DAT
M1_GIGA
M1_RXD[
M1_RXD[
M1_RXD[
M0_RXD[
M1_ACTI
BIT_LED
M1_COL M1_RXD[
M0_CRS M1_RBC0
M0_RXD
VE_LED
A[31]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
7]
3]
4]
V
7]
M1_RXD[
M0_RXD[
M0_ACTI
M_MDIO
M1_RXD
M0_RXE
VE_LED
GND
GND
GND
Data Sheet
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
6]
1]
0]
3]
1]
0]
V
R
AA
AC
AD
AF
AB
AE
W
M
G
L
H
J
N
R
U
A
B
C
D
E
K
P
V
Y
F
T