ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 105

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

13.1.1
The timing of address, data and control are all related to the system clock which is also used by the external
SSRAM to clock these signals. Therefore the propagation delay of the clock to the ZL50110/11/12/14 and the
SSRAM must be matched to within 250 ps, worst case conditions. Trace lengths of theses signals must also be
minimized (<100 mm) and matched to ensure correct operation under all conditions.
13.1.2
The GMII interface passes data to and from the ZL50110/11/12/14 with their related transmit and receive clocks. It
is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related
signals and their clock are kept to the same length. By doing this the skew between individual signals and their
related clock will be minimized.
13.1.3
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data
rate outputs and therefore must be treated with the same care extended to the other interfaces with particular
reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous
clocking schemes and as a result of this the input clock traces to the ZL50110/11/12/14 devices should be treated
with care.
13.1.4
Particular effort should be made to minimize crosstalk from ZL50110/11/12/14 outputs and ensuring fast rise time to
these inputs.
In Summary:
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13.2
The CPU_TA output signal from the ZL50110/11/12/14 is a critical handshake signal to the CPU that ensures the
correct completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the
circuit shown in Figure 50 - CPU_TA Board Circuit is implemented in systems operating above 40 MHz bus
frequency to ensure robust operation under all conditions.
The following external logic is required to implement the circuit:
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Place series termination resistors as close to the pins as possible
Minimize output capacitance
Keep common interface traces close to the same length to avoid skew
Protect input clocks and signals from crosstalk
74LCX74 dual D-type flip-flop (one section of two)
74LCX08 quad AND gate (one section of four)
74LCX125 quad tri-state buffer (one section of four)
4K7 resistor x2
CPU TA Output
TDM Interface - special considerations during layout
External Memory Interface - special considerations during layout
GMAC Interface - special considerations during layout
Summary
ZL50110/11/12/14
Zarlink Semiconductor Inc.
105
Data Sheet