AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 95

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

Table 19
Mode
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
9.4.1
The AN983B/BX provides receive and transmit descriptors for packet buffering and management.
Descriptors and receive buffers addresses must be longword alignment
Table 20
RDES0
RDES1
RDES2
RDES3
RDES0
RDES0
RDES0
Data Sheet
31 ------------------------------------------------------------------------------------------------------------------------------
0
Own
Buffer1 address (DW boundary)
Buffer2 address (DW boundary)
Registers Access Types (cont’d)
Receive Descriptor Descriptions
Receive Descriptor Table
Symbol Description Hardware (HW)
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Status
---
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the HW,
the register will be cleared due to a HW
mechanism.
Registers and Descriptors DescriptionDescriptors and Buffer Management
Control
Offset
00
95
H
Buffer2 byte-count
Description Software (SW)
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is readable and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is readable and writable by SW.
Buffer1 byte-count
Rev. 1.81, 2005-12-15
AN983B/BX
Reset Value
xxxx xxxx
H