AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 26

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AN983B-BG-T-V8

Manufacturer Part Number
AN983B-BG-T-V8
Description
IC PCI TO ETHERNET LAN 128-PQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of AN983B-BG-T-V8

Applications
Ethernet Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
128-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AN983BBGTV8
SP000074652

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AN983B-BG-T-V8
Manufacturer:
Infineon Technologies
Quantity:
10 000
7.5.1
In the MAC (Media Access Control) portion of AN983B/BX, it incorporates the essential protocol requirements for
operating as an IEEE802.3 and Ethernet compliant node.
Table 4
Field
Preamble
Start Frame Delimiter
Destination Address
Source Address
Length/Type
Data
CRC
1) If padding is disabled (TDES1 bit23), the data field may be shorter than 46 bytes.
Transmit Data Encapsulation
The differences between the encapsulation and a MAC frame while operating in the 100BASE-TX mode are listed
as follow:
1. The first byte of the preamble is replaced by the JK code according to the IEE802.3u, clause 24.
2. After the CRC field of the MAC frame, the AN983B/BX inserts the TR code according to the IEE802.3u, clause
Receive Data Decapsulation
When operating in 100BASE-TX mode the AN983B/BX detects a JK code for a preamble as well as a TR code
for the packet end. If a JK code is not detected, the AN983B/BX will abort this frame receiving and wait for a new
JK code detection. If a TR code is not detected, the AN983B/BX will report a CRC error.
Deferring
The Inter-Frame Gap (IFG) time is divided into two parts:
1. IFG1 time (64-bit time): If a carrier is detected on the medium during this time, the AN983B/BX will reset the
2. IFG2 time (32-bit time): After counting the IFG2 time the AN983B/BX will access the channel even though a
Collision Handling
The scheduling of re-transmissions is determined by a controlled randomization process called “truncated binary
exponential back-off”. At the end of enforcing a collision (jamming), the AN983B/BX delays before attempting to
re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the
nth re-transmission attempt is chosen as a uniform distributed integer in the range:
0 ≤ r < 2
Data Sheet
24.
IFG1 time counter and restart to monitor the channel for an idle again.
carrier has been sensed on the network.
k
, where k = min. (n, 10)
MAC Operation
Format
26
Description
A 7-byte field of (10101010b)
A 1-byte field of (10101011b)
A 6-byte field
A 6-byte field
A 2-byte field indicated the frame is in IEEE802.3
format or Ethernet format.IEEE802.3 format: 0000H ~
05DCH for Length field Ethernet format: 05DD ~ FFFFH
for Type field
46
A 32-bit cyclic redundant code for error detection
1)
~ 1500 bytes of data information
Functional Descriptions
Rev. 1.81, 2005-12-15
AN983B/BX

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