AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 9

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

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FIFO
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PCI I/F
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EEPROM/Boot ROM I/F
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MAC/Physical
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LED Display
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Data Sheet
Supports for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
PCI Specification 2.2 compliant
ACPI and PCI power management Ver.1.1 compliant
Supports PC99 wake on LAN
Provides two independent long FIFOs with 2k bytes each for transmission and receiving
Pre-fetch up to two transmit packets to minimize inter frame gap (IFG) to 0.96 µs
Retransmit collided packet without reload from host memory within 64 bytes
Automatically retransmit FIFO under-run packet with maximum drain threshold until 3 times retry failure and
that will not influence the registers and transmit threshold of next packet
Provides 32-bit PCI bus master data transfer
Supports PCI clock with frequency from 0 Hz to 33 MHz
Supports network operation with PCI system clock from 20 MHz to 33 MHz
Provides performance meter, PCI bus master latency timer, for tuning the threshold to enhance the
performance
Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization
Supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-
invalidate command while being bus master
Supports big or little endian byte ordering
Provides write-able Flash ROM and EPROM as boot ROM with size up to 128 KB
Provides PCI to access boot ROM by byte, word, or double word
Re-write Flash boot ROM through I/O port by programming register
Provides serial interface for read/write 93C46/66 EEPROM
Automatically load device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and
Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment.
Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
Provides Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes
Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbit/s
Provides transmit wave-shaper, receives filters, and adaptive equalizer
Provides MLT-3 transceiver with DC restoration for Base-line wander compensation
Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic
Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
Supports external transmit transformer with turn ratio 1:1
Supports external receive transformer with turn ratio 1:1
3 LED displays scheme provided:
– 100 Mbit/s (on) or Speed 10 (off)
– Link (keeps on when link ok) or Activity (will be blinking with 10 Hz when receiving or transmitting but not
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
4 LED displays scheme provided:
– 100 Mbit/s and Link (keep on when link and 100 Mbit/s)
– 10 Mbit/s and Link (keep on when link and 10 Mbit/s)
– Activity (will be blinking with 10 Hz when receiving or transmitting but not collision)
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
collision)
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Rev. 1.81, 2005-12-15
AN983B/BX
Features