AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 58

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

Field
TS
RS
NISS
AISS
Res
FBE
Res
Data Sheet
Bits
22:20
19:17
16
15
14
13
12
Type
ro
ro
ro/lh
ro/lh
ro
ro/lh
ro
Description
Transmit State
Report the current transmission state only, no interrupt will be generated.
000
001
010
011
100
101
110
111
Receive State
Report current receive state only, no interrupt will be generated.
000
001
010
011
100
101
110
111
Normal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 16 of
ACSR5)
bit0, transmit completed interrupt
bit2, transmit descriptor unavailable
bit6, receive descriptor interrupt
Note: lh: High Latching and cleared by writing 1
Abnormal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 15 of
ACSR5)
bit1, transmit process stopped
bit3, transmit jabber timer time-out
bit5, transmit under-flow
bit7, receive descriptor unavailable
bit8, receive processor stopped
bit9, receive watchdog time-out
bit11, general purpose timer time-out
bit13, fatal bus error
Note: lh: High Latching and cleared by writing 1
Reserved
Fatal Bus Error
Note: lh: High Latching and cleared by writing 1
1
Reserved
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(see bits 25~23 of CSR5) AN983B/BX will disable all bus access.
The way to recover parity error is by setting software reset.
, stop
, read descriptor
, transmitting
, FIFO fill read the data from memory and put into FIFO
, reserved
, reserved
, suspended, unavailable transmit descriptor or FIFO overflow
, write descriptor
, stop
, read descriptor
, check this packet and pre-fetch next descriptor
, wait for receiving data
, suspended
, write descriptor
, flush the current FIFO
, FIFO drain. move data from receiving FIFO into memory
, while any of parity error master abort, or target abort is occurred
58
Rev. 1.81, 2005-12-15
AN983B/BX