AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 63

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

Field
Res
NIE
AIE
Res
FBEIE
Res
GPTIE
Res
RWTIE
RSIE
RUIE
RCIE
TUIE
Res
TJTTIE
TDUIE
TPSIE
TCIE
Data Sheet
Bits
31:17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
ro
rw
rw
ro
rw
ro
rw
ro
rw
rw
rw
rw
rw
ro
rw
rw
rw
rw
Description
Reserved
Normal Interrupt Enable
1
Abnormal Interrupt Enable
1
Reserved
Fatal Bus Error Interrupt Enable
1
Reserved
General Purpose Timer Interrupt Enable
1
Reserved
Receive Watchdog Time-out Interrupt Enable
1
Receive Stopped Interrupt Enable
1
Receive Descriptor Unavailable Interrupt Enable
1
Receive Completed Interrupt Enable
1
Transmit Under-flow Interrupt Enable
1
Reserved
Transmit Jabber Timer Time-out Interrupt Enable
1
Transmit Descriptor Unavailable Interrupt Enable
1
Transmit Processor Stopped Interrupt Enable
1
Transmit Completed Interrupt Enable
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
B
B
B
B
B
B
interrupt
timer expired interrupt
time-out interrupt
interrupt
unavailable interrupt
interrupt
interrupt
time-out interrupt
unavailable interrupt
stopped interrupt
interrupt.
, combine this bit and bit 15 of CSR7 to enable transmit under-flow
, combine this bit and bit 15 of CSR7 to enable transmit jabber timer
, combine this bit and bit 16 of CSR7 to enable transmit completed
, enable all the normal interrupt bits (see bit16 of CSR5)
, enable all the abnormal interrupt bits (see bit15 of CSR5)
, combine this bit and bit 15 of CSR7 to enable fatal bus error
, combine this bit and bit 15 of CSR7 to enable general-purpose
, combine this bit and bit 15 of CSR7 to enable receive watchdog
, combine this bit and bit 15 of CSR7 to enable receive stopped
, combine this bit and bit 15 of CSR7 to enable receive descriptor
, combine this bit and bit 16 of CSR7 to enable receive completed
, combine this bit and bit 16 of CSR7 to enable transmit descriptor
, combine this bit and bit 15 of CSR7 to enable transmit processor
63
Rev. 1.81, 2005-12-15
AN983B/BX