AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 28

• Manufacturer Part Number: AN983B-BG-T-V8
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983B-BG-T-V8

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AN983BBGTV8; SP000074652

AN983B/BX
Functional Descriptions
100BASE-TX Receiving Operation
Regarding the 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA,
and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turns
ratio of 1: 1. It includes the adaptive equalizer, baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ,
and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B.
Adaptive Equalizer and Baseline Wander
The high-speed signals over the unshielded (or shielded) twisted Pair cable will induce the amplitude attenuation
and phase shifting. Furthermore, these effects are dependent on the signal frequency, cable type, cable length
and the connectors of the cabling. So a reliable adaptive equalizer and baseline wander to compensate all the
amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to
perform these functions.
MLT3 to NRZI Decoder and PLL for Data Recovery
After receiving the proper MLT3 signals, the transceiver converts the MLT3 to NRZI code for further processing.
After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type
in 125 MHz are passed to the Phase Lock Loop circuits to extract out the original data and the synchronous clock.
Data Conversions of NRZI to NRZ and Serial to Parallel
After data recovered, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit
stream. This serial bit stream will be packed to parallel 5B type for further processing.
De-scrambling and Decoding of 5B/4B
The parallel 5B type data is passed to de-scrambler and 5B/4B decoder to return their original MII nibble type data.
Carrier Sensing
Carrier Sense (CRS) signal is asserted when the transceiver detects any 2 non-contiguous zeros within any 10bit
boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected.
In half duplex mode, CRS is asserted during packet transmission or reception. But in full duplex mode, CRS is
asserted only during packet reception.
10BASE-T Transmission Operation
It includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function, the transmit
wave-shaper, and line driver described in the section of “Wave-Shaper and Media Signal Driver” of “100BASE-T
Transmission Operation”. It also provides Collision detection and SQE test for half duplex application.
10BASE-T Receive Operation
It includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder, and
serial to parallel converter.
Loop-back Operation of Transceiver
The transceiver provides internal loop-back (also called transceiver loop-back) operation for both the 100BASE-
TX and 10BASE-T operations. Setting bit 14 of PHY register 0 to 1 can enable the loop-back operation. In this
loop-back operation, PHY will not transmit packets (but PHY will still send MLT3 for Idle).
In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI
converter then loop-back to the receiving path into the input of NRZI to NRZ converter.
In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back from the output of the
Manchester encoder into the input of Phase Lock Loop circuit of receiving path.
Data Sheet
28
Rev. 1.81, 2005-12-15