AN983B-BG-T-V8 Infineon Technologies, AN983B-BG-T-V8 Datasheet - Page 72

no-image

AN983B-BG-T-V8

Manufacturer Part Number
AN983B-BG-T-V8
Description
IC PCI TO ETHERNET LAN 128-PQFP
Manufacturer
Infineon Technologies
Datasheet

Specifications of AN983B-BG-T-V8

Applications
Ethernet Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
128-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AN983BBGTV8
SP000074652

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AN983B-BG-T-V8
Manufacturer:
Infineon Technologies
Quantity:
10 000
Assistant CSR7 (Interrupt Enable Register 2)
ACSR7_CSR17
Assistant CSR7 (Interrupt Enable Register 2)
Field
TEIE
REIE
LCIE
TDIE
Res
PFRIE
Res
ANISE
AAIE
Res
FBEIE
Res
GPTIE
Res
RWTIE
RSIE
RUIE
Data Sheet
Bits
31
30
29
28
27
26
25:17
16
15
14
13
12
11
10
9
8
7
Type
rw
rw
rw
rw
ro
rw
ro
rw
rw
ro
rw
ro
rw
ro
rw
rw
rw
Description
Transmit Early Interrupt Enable
Receive Early Interrupt Enable
Link Status Change Interrupt Enable
Transmit Deferred Interrupt Enable
Reserved
PAUSE Frame Received Interrupt Enable
Reserved
Added Normal Interrupt Summary Enable
1
Added Abnormal Interrupt Summary Enable
1
Reserved
Fatal Bus Error Interrupt Enable
1
Reserved
General Purpose Timer Interrupt Enable
1
Reserved
Receive Watchdog Time-out Interrupt Enable
1
Receive Stopped Interrupt Enable
1
Receive Descriptor Unavailable Interrupt Enable
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
interrupt summary (bit 16 of CSR5)
interrupt summary
interrupt
timer expired interrupt
time-out interrupt
interrupt
unavailable interrupt
, adds the interrupts of bit 26, 28 and 29 of ACSR7 to the abnormal
, adds the interrupts of bit 30 and 31 of ACSR7 to the normal
, combine this bit and bit 15 of CSR7 to enable fatal bus error
, combine this bit and bit 15 of CSR7 to enable general-purpose
, combine this bit and bit 15 of CSR7 to enable receive watchdog
, combine this bit and bit 15 of CSR7 to enable receive stopped
, combine this bit and bit 15 of CSR7 to enable receive descriptor
Offset
84
72
H
Rev. 1.81, 2005-12-15
AN983B/BX
Reset Value
0000 0000
H

Related parts for AN983B-BG-T-V8