PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 6

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

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Pericom Semiconductor – Confidential
NEXT CAPABILITY POINTER REGISTER – OFFSET B0h ................................................................ 57
PCI EXPRESS CAPABILITY REGISTER – OFFSET B0h ................................................................... 57
DEVICE CAPABILITY REGISTER – OFFSET B4h............................................................................. 57
DEVICE CONTROL REGISTER – OFFSET B8h................................................................................. 58
DEVICE STATUS REGISTER – OFFSET B8h..................................................................................... 59
LINK CAPABILITY REGISTER – OFFSET BCh ................................................................................. 59
LINK CONTROL REGISTER – OFFSET C0h...................................................................................... 60
LINK STATUS REGISTER – OFFSET C0h.......................................................................................... 60
SLOT CAPABILITY REGISTER – OFFSET C4h ................................................................................. 61
SLOT CONTROL REGISTER – OFFSET C8h ..................................................................................... 61
SLOT STATUS REGISTER – OFFSET C8h ......................................................................................... 62
XPIP CONFIGURATION REGISTER 0 – OFFSET CCh..................................................................... 62
XPIP CONFIGURATION REGISTER 1 – OFFSET D0h ..................................................................... 62
XPIP CONFIGURATION REGISTER 2 – OFFSET D4h ..................................................................... 62
HOT SWAP SWITCH DEBOUNCE COUNTER – OFFSET D4h......................................................... 64
CAPABILITY ID REGISTER – OFFSET D8h ...................................................................................... 64
NEXT POINTER REGISTER – OFFSET D8h ...................................................................................... 64
VPD REGISTER – OFFSET D8h ......................................................................................................... 64
VPD DATA REGISTER – OFFSET DCh.............................................................................................. 64
RESERVED REGISTERS – OFFSET E0h – ECh ................................................................................. 65
MESSAGE SIGNALED INTERRUPTS ID REGISTER – F0h............................................................... 65
NEXT CAPABILITIES POINTER REGISTER – F0h............................................................................ 65
MESSAGE CONTROL REGISTER – OFFSET F0h ............................................................................. 65
MESSAGE ADDRESS REGISTER – OFFSET F4h .............................................................................. 65
MESSAGE UPPER ADDRESS REGISTER – OFFSET F8h................................................................. 65
MESSAGE DATA REGISTER – OFFSET FCh..................................................................................... 66
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h .............................. 66
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER – OFFSET 100h .................. 66
NEXT CAPABILITY OFFSET REGISTER – OFFSET 100h ................................................................ 66
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................... 66
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h ...................................................... 66
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................... 67
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110h......................................................... 67
CORRECTABLE ERROR MASK REGISTER – OFFSET 114h ............................................................ 67
ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h........................ 68
HEADER LOG REGISTER 1 – OFFSET 11Ch .................................................................................... 68
HEADER LOG REGISTER 2 – OFFSET 120h..................................................................................... 68
HEADER LOG REGISTER 3 – OFFSET 124h..................................................................................... 68
HEADER LOG REGISTER 4 – OFFSET 128h..................................................................................... 68
SECONDARY UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 12Ch ........................... 68
SECONDARY UNCORRECTABLE ERROR MASK REGISTER – OFFSET 130h ............................... 69
SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 134h ........................ 69
SECONDARY ERROR CAPABILITY AND CONTROL REGISTER – OFFSET 138h.......................... 70
SECONDARY HEADER LOG REGISTER – OFFSET 13Ch – 148h.................................................... 70
RESERVED REGISTER – OFFSET 14Ch ............................................................................................ 70
VC CAPABILITY ID REGISTER – OFFSET 150h ............................................................................... 70
VC CAPABILITY VERSION REGISTER – OFFSET 150h ................................................................... 70
NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 71
PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 71
PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 71
PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 71
PORT VC STATUS REGISTER – OFFSET 15Ch................................................................................. 71
Page 6 of 144
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110