PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 37

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

7.4.16 I/O LIMIT REGISTER – OFFSET 1Ch
7.4.17 SECONDARY STATUS REGISTER – OFFSET 1Ch
Pericom Semiconductor – Confidential
BIT
1:0
3:2
7:4
BIT
9:8
11:10
15:12
BIT
20:16
21
22
23
24
26:25
27
FUNCTION
32-bit I/O Addressing
Support
Reserved
I/O Base
FUNCTION
32-bit I/O Addressing
Support
Reserved
I/O Base
FUNCTION
Reserved
66MHz Capable
Reserved
Fast Back-to-Back Capable
Master Data Parity Error
Detected
DEVSEL_L Timing
(medium decoding)
Signaled Target Abort
TYPE
TYPE
TYPE
RWC
RWC
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
01: Indicates PI7C9X110 supports 32-bit I/O addressing
Reset to 01
Reset to 00
Indicates the I/O base (0000_0000h)
Reset to 0000
DESCRIPTION
01: Indicates PI7C9X110 supports 32-bit I/O addressing
Reset to 01
Reset to 00
Indicates the I/O Limit (0000_0FFFh)
Reset to 0000
DESCRIPTION
Reset to 00000
Indicates PI7C9X110 is 66MHz capable
Reset to 1
Reset to 0
FORWARD BRIDGE: reset to 1 when secondary bus is in PCI mode
(supports fast back-to-back transactions)
REVERSE BRIDGE: reset to 0 (does not support fast back-to-back
transactions)
This bit is set if its parity error enable bit is set and either of the conditions
occur on the primary:
FORWARD BRIDGE –
•
•
•
REVERSE BRIDGE –
•
•
Reset to 0
These bits apply to forward bridge only.
01: medium DEVSEL_L decoding
Reset to 01 when forward mode or 00 when reverse mode.
FORWARD BRIDGE –
Bit is set when PI7C9X110 signals target abort
REVERSE BRIDGE –
Bit is set when PI7C9X110 completes a request using completer abort
completion status
Reset to 0
Detected parity error when receiving data or split response for read
Observes S_PERR_L asserted when sending data or receiving split
response for write
Receives a split completion message indicating data parity error
occurred for non-posted write
Receives a completion marked poisoned
Poisons a write request
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110