PI7C9X110BNBE Pericom Semiconductor, PI7C9X110BNBE Datasheet - Page 134

• Manufacturer Part Number: PI7C9X110BNBE
• Description: IC PCIE TO PCI REV BRG 160LFBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X110BNBE

• Applications: PCI-to-PCI Bridge
• Interface: I²C
• Voltage - Supply: 1.8 V
• Package / Case: 160-LBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

14
14.1 INSTRUCTION REGISTER
PI7C9X110 requires the fundamental reset (PERST_L) input for internal logic when it is set as forward bridge
mode. PI7C9X110 requires the PCI reset (RESET_L) input when it is set as reverse bridge mode. Also,
PI7C9X110 has a power-on-reset (POR) circuit to detect VDDCAUX power supply for auxiliary logic control.
A cold reset is a fundamental or power-on reset that occurs right after the power is applied to PI7C9X110 (during
initial power up). See section 7.1.1 of PCI Express to PCI Bridge Specification, Revision 1.0 for details.
A warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to
PI7C9X110.
A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to PI7C9X110.
PI7C9X110 will enter to training control reset when it receives two consecutive TS1 or TS2 order-sets with reset bit
set.
If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status. PI7C9X110
discards all transactions and returns all logic and registers to initial state except the sticky registers.
Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X110 will generate PCI reset
(RESET_L) to the downstream devices on the PCI bus in forward bridge mode. The PCI reset de-assertion follows
the de-assertion of the reset received from PCIe interface. The reset bit of Bridge Control Register may be set
depending on the application. PI7C9X110 will tolerant to receive and process SKIP order-sets at an average
interval between 1180 to 1538 Symbol Times. PI7C9X110 does not keep PCI reset active when VD33 power is off
even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down resistor on its application
board to ensure PCI reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management
Specification Revision 1.1).
In reverse bridge mode, PI7C9X110 generates fundamental reset (PERST_L) and then 1024 TS1 order-sets with
reset bit set when PCI reset (RESET_L) is asserted to PI7C9X110. PI7C9X110 has scheduling skip order-set for
insertion at an interval between 1180 and 1538 Symbol Times.
PI7C9X110 transmits one Electrical Idle order-set and enters to Electrical Idle.
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X110 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI,
TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the
PCI resource is operating PCI bus cycles.
Pericom Semiconductor – Confidential
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
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Cold Reset:
Warm Reset:
Hot Reset:
DL_DOWN Reset:
Page 134 of 144
April 2010, Revision 3.0
PCIe-to-PCI Reversible Bridge
PI7C9X110