FQM1-TER01 Omron, FQM1-TER01 Datasheet - Page 232

• Manufacturer Part Number: FQM1-TER01
• Description: 5M 4COND 22AWG TPE ST MALE M12
• Manufacturer: Omron

Specifications of FQM1-TER01

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: FQM1TER01

Pulse Inputs
Counter values
High-speed counter PV storage locations
Latch inputs
Control
method
Counter reset
Mea-
sure-
ment
mode
Target value comparison
Range comparison
Counter movements
(mode 1)
Counter frequency
(mode 2)
Measurement storage location
for above measurements
• Select mode 1 or mode 2 in the System Setup.
• Measurement starts when the Measurement Start Bit (A860.02 for high-speed counter 1 or A861.02 for
• The Measuring Flag (A858.06 for high-speed counter 1 or A859.06 for high-speed counter 2) will be ON dur-
high-speed counter 2) is turned ON.
ing the measurement.
Item
Linear Counter: 8000 0000 to 7FFF FFFF hex
Circular Counter: 0000 0000 to Circular maximum count (hex)
(The circular maximum count is set in the System Setup between 0000
0001 and FFFF FFFF hex.)
High-speed counter 1: A851 (upper bytes) and A850 (lower bytes)
High-speed counter 2: A853 (upper bytes) and A852 (lower bytes)
These values can be used for target-value comparison interrupts or
range-comparison bit pattern outputs.
Note The PVs are refreshed during the Motion Control Module’s I/O
Data storage format: 8-digit hexadecimal
• Linear Counter: 8000 0000 to 7FFF FFFF hex
• Circular Counter: 0000 0000 to Circular maximum count
There are two latch inputs. One latch input can be for each high-speed
counter or both latch inputs can be used for one high-speed counter. It is
also possible for both high-speed counters to share one latch input.
The latched PV can be read with the PRV(881) instruction.
Register up to 48 target values and interrupt tasks.
Register up to 16 upper limits, lower limits, and output bit patterns.
Phase Z Signal + Software Reset
The counter is reset on the phase-Z signal if the Reset Bit is ON.
Software Reset
The counter is reset when the Reset Bit is turned ON.
Note The counter reset method is set in System Setup.
Reset Bits
A860.01 is the Reset Bit for high-speed counter 1 and A861.01 is the Reset
Bit for high-speed counter 2.
Measures the change in the high-speed counter’s PV for the set sampling
time or each cycle.
Sampling time: 1 to 9,999 ms
Movement (absolute value): 0000 0000 to FFFF FFFF hex
The frequency is calculated from the PV between 0 and 500,000 Hz.
High-speed counter 1: A855 (upper bytes) and A854 (lower bytes)
High-speed counter 2: A857 (upper bytes) and A856 (lower bytes)
Note The high-speed counter value can also be read with the PRV(881)
Stored Data
Movement: 8-digit hexadecimal
Frequency: 8-digit hexadecimal
Note The data is refreshed during the Motion Control Module’s I/O refresh
refresh. The PVs can also be read with the PRV(881) instruction.
instruction.
period.
Specification
Section 7-5
205