ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet - Page 96

• Manufacturer Part Number: ST72C334N2B6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2B6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: SDIP-56
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72334J/N, ST72314J/N, ST72124J
8-BIT A/D CONVERTER (ADC) (Cont’d)
6.7.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
to V
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (V
V
version result in the DR register is 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
6.7.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion
phases as shown in Figure 57:
While the ADC is on, these two phases are contin-
uously repeated.
At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.
6.7.3.4 Software Procedure
Refer to the control/status register (CSR) and data
register (DR) in Section 6.7.6 for the bit definitions
and to Figure 57 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC
clock periods (1/f
96/125
SSA
AIN
Sample capacitor loading
[duration: t
During this phase, the V
measured is loaded into the C
capacitor.
A/D conversion
[duration: t
During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and
disconnected from the analog input pin to get
the optimum A/D conversion accuracy.
DDA
is the maximum recommended impedance
(low-level voltage reference) then the con-
the
(high-level voltage reference) then the
LOAD
CONV
C
SAMPLE
ADC
]
]
AIN
=2/f
AIN
) is lower than or equal to
CPU
) is greater than or equal
sample
AIN
).
input voltage to be
SAMPLE
capacitor
sample
is
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the CSR register:
ADC Conversion
In the CSR register:
When a conversion is complete
A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.
Figure 57. ADC Conversion Timings
6.7.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed and between single shot conversions..
6.7.5 Interrupts
None
Mode
WAIT
HALT
ADON
HOLD
CONTROL
– Select the CH[3:0] bits to assign the analog
– Set the ADON bit to enable the A/D converter
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains
channel to convert.
and to start the first conversion. From this time
on, the ADC performs a continuous conver-
sion of the selected channel.
valid until the next conversion has ended.
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilisation time
before accurate conversions can be
performed.
t
LOAD
t
CONV
COCO BIT SET
ADCCSR WRITE
OPERATION