ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet - Page 33

• Manufacturer Part Number: ST72C334N2B6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2B6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: SDIP-56
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

4.4 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
CLOCK RESET AND SUPPLY REGISTER
(CRSR)
Read/Write
Reset Value: 000x 000x (00h)
Bit 7:5 = Reserved, always read as 0.
Bit 4 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bit 3 = Reserved, always read as 0.
Bit 2 = CSSIE Clock security syst
This bit enables the interrupt when a disturbance
is detected by the Clock Security System (CSSD
bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
When the CSS is disabled by OPTION BYTE, the
CSSIE bit has no effect.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
7
0
(Hex.)
002Bh
0
CRSR
Reset Value
Register
0
Label
LVD
RF
0
7
0
CSS
.
IE
interrupt enable
CSS
6
0
D
WDG
RF
0
5
0
Bit 1 = CSSD Clock security system detection
This bit indicates that the safe oscillator of the
Clock Security System block has been selected by
hardware due to a disturbance on the main clock
signal (f
a read of the CRSR register when the original os-
cillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by OPTION BYTE, the
CSSD bit value is forced to 0.
Bit 0 = WDGRF Watchdog reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or a LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.
Application notes
In case the LVDRF flag is not cleared upon anoth-
er RESET type occurs (extern or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this condition, a watchdog reset can be detect-
ed by the software while an external reset not.
LVDRF
4
x
ST72334J/N, ST72314J/N, ST72124J
External RESET pin
OSC
RESET Sources
Watchdog
). It is set by hardware and cleared by
LVD
3
0
CFIE
2
0
LVDRF
CSSD
1
0
0
0
1
WDGRF
WDGRF
33/125
0
X
x
0
1