ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet - Page 26

• Manufacturer Part Number: ST72C334N2B6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2B6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: SDIP-56
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72334J/N, ST72314J/N, ST72124J
4.2 RESET SEQUENCE MANAGER (RSM)
The reset sequence manager includes three RE-
SET sources as shown in Figure 15:
These sources act on the RESET PIN and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in Figure 14:
Figure 15. Reset Block Diagram
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EXTERNAL RESET SOURCE pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Delay depending on the RESET source
4096 CPU clock cycle delay
RESET vector fetch
RESET
V
DD
R
ON
f
CPU
The 4096 CPU clock cycle delay allows the oscil-
lator to stabilise and ensures that recovery has
taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. RESET Sequence Phases
DELAY
4096 CLOCK CYCLES
INTERNAL RESET
RESET
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
VECTOR
FETCH