ST72C334N2B6 STMicroelectronics, ST72C334N2B6 Datasheet - Page 36

• Manufacturer Part Number: ST72C334N2B6
• Description: Microcontrollers (MCU) Flash 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72C334N2B6

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: SDIP-56
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / Rohs Status: No

ST72334J/N, ST72314J/N, ST72124J
5 INTERRUPTS & POWER SAVING MODES
5.1 INTERRUPTS
The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 26.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).
When an interrupt has to be serviced:
– Normal processing is suspended at the end of
– The PC, X, A and CC registers are saved onto
– The I bit of the CC register is set to prevent addi-
– The PC is then loaded with the interrupt vector of
The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.
Priority management
By default, the interrupt being serviced cannot be
interrupted because the I bit is set by hardware
when entering an interrupt routine.
If several interrupts are simultaneously pending, a
hardware priority defines which one will be serv-
iced first (see the Interrupt Mapping Table).
Non Maskable Software Interrupts
This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 26.
Interrupts and Low power mode
All interrupts allow the processor to leave the Wait
low power mode. Only external and specific men-
tioned interrupts allow the processor to leave the
36/125
the current instruction execution.
the stack.
tional interrupts.
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).
Halt low power mode (refer to the “Exit from HALT“
column in the Interrupt Mapping Table).
External Interrupts
External interrupt vectors can be loaded in the PC
register if the corresponding external interrupt oc-
curred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.
The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.
Warning: The type of sensitivity defined in the
Miscellaneous or Interrupt register (if available)
applies to the EI source. In case of an ANDed
source (as described on the I/O ports section), a
low level on an I/O pin configured as input with in-
terrupt, masks the interrupt request even in case
of rising-edge sensitivity.
Peripheral Interrupts
Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control
If any of these two conditions is false, the interrupt
is latched and thus remains pending.
Clearing an interrupt request is done by:
– writing “0” to the corresponding bit in the status
– an access to the status register while the flag is
Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.
register.
register or
set followed by a read or write of an associated
register.