MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 97

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
10.11
10.12
OR9
OR9(2) — Control Register, Force INFO 2 Transmission
When the device is initialized, this bit is logic 0. When set to a logic 0, the device operates as normal
in all modes. This register bit is only operational in NT modes. In NT modes, the FI2 (force
INFO 2 transmission) allows the software to force an activated NT (state G3) to transmit INFO 2 and
reconfirm synchronization with the received INFO 3; i.e., the NT makes a G3 to G2 state jump, and
on attaining G2 the FI2 bit is automatically reset. The NT then reconfirms INFO 3 and returns to the
G3 state.
OR9(1) — Control Register, T3F8 Enable
When the device is initialized, this bit is a logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit only operates in the TE mode. By setting this bit to 1, the T3EXP control bit
in NR2(1) is allowed to operate in F8. Hence, when in F8 and T3 expires, the device can be forced
to go to the F3 state. This is in accordance with the ETSI ETS 300012 S/T–interface specification.
OR9(0) — Control Register, T3F6 Disable
When the device is initialized, this bit is logic 0. When set to a logic 0, the device operates as normal
in all modes. This bit only operates in the TE mode. By setting this bit to a 1, the T3EXP control bit
in NR2(1) is disabled from operating in F6. Hence, when in F6 and T3 expires, the device will not
be forced to go to the F3 state, but will stay in F6 and transition to F7 when INFO 4 is confirmed.
This is in accordance with the ETSI ETS 300012 S/T–interface specification.
OR15
OR15(7) — Overlay Register Enable
When set to a logic 1, the second set of overlay registers is enabled. The overlay register map allows
access to the TSA registers required by the IDL2 and also to a GCI control register.
OR15(5:0) — Device Revision Identification, Rev (5:0)
The Rev (5:0) bits indicate the revision status of the device. These bits are read only and can only
be modified by altering the device masks. Rev (5:0) is set to 11H for G20R1 mask set, and 03H for
F57J4 mask set.
OR15
OR9
Register
Overlay
Enable
(7)
(7)
Freescale Semiconductor, Inc.
For More Information On This Product,
(6)
(6)
Go to: www.freescale.com
Rev 5
(5)
(5)
MC145574
Rev 4
(4)
(4)
Rev 3
(3)
(3)
mission
Trans–
INFO2
Force
Rev 2
(2)
(2)
Enable
Rev 1
T3F8
(1)
(1)
Disable
Rev 0
T3F6
(0)
(0)
10–7