MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 71

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
8.3
8.4
NR1
This register is a read only register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 1 (NR1) follows.
NR1(3) — Activation Indication (AI)
This bit is set by the MC145574 when the loop is fully activated. Thus, when the MC145574 is config-
ured as an NT, this bit is set when it is transmitting INFO 4 and receiving INFO 3. Conversely, when
the MC145574 is configured as a TE, this bit is set when it is transmitting INFO 3 and receiving INFO
4. Note that NR1(3) is a read only bit.
NR1(2) — Error Indication (EI)
NR1(2) is set by the MC145574 S/T transceiver to indicate an error condition has been detected by
the activation state machine of the transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. The low–to–high level transition of the EI bit corresponds to the EI1 error indication
reporting, while the high–to–low level transition of the EI bit corresponds to the EI2 error indication
reporting recovery. Note that NR1(2) is a read only bit.
NR1(1) — NT: Not Applicable
In the TE mode of operation, this bit is set by the MC145574 S/T transceiver whenever it detects
multiframing from the NT. This bit will be set low if multiframing synchronization is lost and will return
high when synchronization is re–acquired. This bit applies only to TE–configured devices. Note that
NR1(1) is a read only bit.
NR1(0) — Frame Sync (FS)
NR1(0) is set high by the MC145574 S/T transceiver when frame synchronization is achieved. NR1(0)
is reset by the MC145574 whenever frame synchronization is lost. Note that NR1(0) is a read only
bit.
NR2
This register is a read/write register and can be cleared by application of either a hardware or software
reset. A per–bit description of nibble register 2 (NR2) is as follows.
NR2(3) — Activation Request (AR)
When NR2(3) is set to 1, an activation request input is passed to the activate state machine within
the MC145574 S/T transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605.
If the transceiver is in the idle state (i.e., transmitting and receiving INFO 0) and is configured as an
NT, then AR causes INFO 2 to be sent out on the transmit side of the S/T–interface. Alternatively,
if the chip is configured as a TE and is in the idle state, then writing a 1 to NR2(3) causes INFO 1
to be sent out. Note that this bit will be returned low by the MC145574 S/T transceiver after its active
NR1
NR2
TE: Multiframing Detection (MD)
Activation Indication
Activation Request
Freescale Semiconductor, Inc.
For More Information On This Product,
b3
b3
Go to: www.freescale.com
rw
ro
NT: Deactivate Request
MC145574
TE: Not Applicable
Error Indication
b2
b2
rw
ro
NT: Not Applicable
TE: Multiframing
Activation Timer
Detection
Expired
b1
b1
rw
ro
NT: NT Terminal Class
Frame Sync
TE: Class
b0
b0
8–3
rw
ro