MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 125

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
18.5.1
TSEN
18.5
D out
DCL
FSC
D in
2
IDL2 TIMING CHARACTERISTICS
IDL2 Master Timing, 8- and 10-Bit Formats
NOTES:
Ref. No.
1. FSC occurs on average every 125 s.
2. The DCL frequency may be 512 kHz, 1.536 MHz, 2.048 MHz, or 2.56 MHz.
3. The duty cycle of DCL is between 45% and 55% when operated in Master Timing mode.
4. In IDL 8– and 10–bit formats, TSEN can be valid during the B1, B2, and D channel timeslots.
10
11
12
13
1
2
3
4
5
6
7
8
9
7
FSC Period
Delay From the Rising Edge of DCL to the Rising Edge of FSC
Delay From the Rising Edge of DCL to the Falling Edge of FSC
DCL Clock Period
DCL Pulse Width High, Nominal
DCL Pulse Width Low
Delay From Rising Edge of DCL to Low–Z and Valid Data on
D out
Delay From Rising Edge of DCL to Data Valid on D out
Delay From Rising Edge of DCL to High–Z on D out
Data Valid on D in Before Falling Edge of DCL (D in Setup Time)
Data Valid on D in After Falling Edge of DCL (D in Hold Time)
Delay From Rising Edge of DCL to TSEN Low
Delay From Falling Edge of DCL to TSEN High
Figure 18–1. IDL2 Master Timing, 8– and 10–Bit Formats
10
12
3
Freescale Semiconductor, Inc.
For More Information On This Product,
5
Go to: www.freescale.com
11
Parameter
MC145574
1
6
4
8
1.536 MHz
2.048 MHz
2.56 MHz
512 kHz
Min
125
391
878
293
220
175
45
25
25
—
—
—
—
—
—
5
13
Typ
125
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9
1953
1074
Max
358
265
215
30
30
55
30
30
30
30
30
—
—
—
Period
Unit
% of
DCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Note
18–3
1
2
3
4