MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 91

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
OR15
10.1
OR0
OR1
OR2
OR3
OR4
OR5
OR5
OR6
OR7
OR8
OR9
Regulator
Reserved
INTRODUCTION
There are eleven overlay registers (OR0 through OR9 and OR15) in the MC145574. The overlay regis-
ters are a second bank of registers available when the overlay register control bit BR15(7) is set to
a logic 1. These overlay registers are in the IDL2 TSA mode used to assign the timeslot used by each
channel (B1, B2, and D) for transmission and reception; OR0 through OR5, OR6, OR7, and OR8
are control registers used in the GCI indirect mode, and OR15 gives the revision number of the S/T
chip.
Register
TSA B1
Overlay
Disable
Enable
Enable
3 V
(7)
TSA B2
S/G Bit
Enable
Enable
Time Slot Assignment for GCI Mode
OVERLAY REGISTER MAP DEFINITION
(6)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 10–1. Overlay Register Map
Disable XTAL
Enable
Enable
TSA D
Rev 5
TCLK
(5)
D out B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
D out B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
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D out D Channel Timeslot Bits (7:0) (IDL2 Mode)
D in B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
D in B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
D in D Channel Timeslot Bits (7:0) (IDL2 Mode)
MC145574
Dual Frame
TE Mode
Enable
Syncs
Rev 4
(4)
Master Mode
D out Open
Enable
Frame
Rev 3
Drain
Long
(3)
Mode Enable
Transmission
GCI Indirect
FIX Enable
8/10 Bit
INFO 2
Select
Rev 2
Force
(2)
S2
Mode Enable
TSEN B1/B2
BCL Enable
NT Terminal
Enable,
Enable
Rev 1
CLK1
T3F8
(1)
S1
D Channel
10
Disable
Enable
Enable
TSEN
Rev 0
CLK0
Sleep
T3F6
(0)
S0
10–1