MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 26

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MC145574AAER2

Manufacturer Part Number
MC145574AAER2
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145574AAER2

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
3–4
3.12.3
3.12.4
3.12.5
A Bit
An S/T frame consists of 48 bauds. In the NT to TE direction, one of these bauds is for the A bit.
The A bit is set to 1 when the S/T loop is in the fully activated state and is set to 0 at all other times.
Thus, when the NT is transmitting INFO 2, the A bit is set to 0. When the NT is transmitting INFO 4,
the A bit is set to 1.
SCP Nomenclature
There are seven nibble registers, 16 byte registers, and 10 overlay registers in the MC145574. These
registers are accessed by means of the SCP. NR1(2) refers to nibble register 1, bit 2. Likewise, BR3(4)
refers to byte register 3, bit 4, and OR5(6) refers to overlay register 5, bit 6.
The overlay registers are a second bank of registers available when the overlay register control bit
BR15(7) is set to logic 1.
SCP Indication of Transmit and Receive States
Note that there are two SCP bits, BR11(5:4), used to signify what INFO state the MC145574 is receiv-
ing. In addition to this, BR11(3:2) are used to signify what INFO state the MC145574 is transmitting.
Refer to Tables 9–2 and 9–3 for a detailed description of these bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
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MC145574
MOTOROLA

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