MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 50

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MC145574AAER2

Manufacturer Part Number
MC145574AAER2
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145574AAER2

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
6–4
6.4
GCI INDIRECT MODE
When control of the SCP interface is available, a pseudo GCI mode can be activated through the
GCI control register. In the indirect mode, the SCP interface operates as normal and the IDL2 interface
operates in a GCI type 2B+D data format mode. This means that the 2B+D data is assembled in a
pseudo GCI frame for transmission, but the C/I, monitor, and A/E fields are high impedance. For recep-
tion, data is recognized in the B and D channels but is ignored in the C/I, M, and A/E channels. The
SCP interface is available as normal.
The following GCI control bits are located in the overlay register set, in OR5 and OR6.
GCI_IND EN, OR6(b2)
At reset, this bit is set to a logic zero; the inactive state (i.e., normal IDL2 mode). When set to a logic
one, the IDL2 port is reconfigured to have the same 2B+D data format as a GCI interface. When GCI
indirect mode is inactive, OR5(2:0) and OR6(1:0) bits are disabled.
CLK(1:0), OR6(b1, b0)
In master mode, these two bits control the output clock frequency of GCI_DCL. CLK(1:0)=0 is the
default state.
D out
FSC
DCL
D in
Freescale Semiconductor, Inc.
For More Information On This Product,
B1
B1
Go to: www.freescale.com
Figure 6–2. GCI Indirect Mode
OR6(b1)
MC145574
CLK1
FSC = 8 kHz
0
0
1
1
Table 6–1. CLK1, CLK0
BASIC GCI CHANNEL IN INDIRECT MODE
GCI Clock Selection
B2
B2
OR6(b0)
DCL = 512 kHz
CLK0
0
1
0
1
125 s
2.048 MHz
2.048 MHz
1.536 MHz
GCI_DCL
512 kHz
D out /D in = 256 kbps
D D
D D
MOTOROLA

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