MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 65

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
7.2.10
7.2.11
7.2.12
7.2.13
7.2.14
7.2.15
7.2.16
7.2.17
7.2.18
7.2.9
CLASS/ECHO_IN
This pin performs two functions dependent on the mode of operation. In the NT1 Star mode, it is the
ECHO_IN input function for use in NT1 Star applications. In the TE master mode, this pin is the class
input used to determine the D channel access class. In all other modes, this input has no defined
function and should be tied to V SS .
FSC/FSR
This pin is bidirectional; the direction depending on whether the device is to be a timing master or
a slave to the IDL2/GCI interfaces. In either case, this pin should be driven with or it generates an
8 kHz frame sync signal. This pin is also the frame sync signal for the IDL2 receive direction (FSR)
when independent frame syncs have been enabled via the SCP interface.
DCL
This pin is the clock pin for the IDL2/GCI interfaces and is either an input or an output depending
on whether the interface is operating as a slave or a master.
D in
This pin is the data input pin for the GCI and IDL2 interfaces.
D out
This pin is the data output pin for the GCI and IDL2 interfaces.
SCP Tx/S0/M0
This pin has three functions. It is the data output pin (SCP Tx) in SCP mode, a timeslot select input
pin (S0) in GCI slave mode, and a mode select pin (M0) in GCI master mode.
SCP Rx/S1/M1
This pin has three functions. It is the data input pin (SCP Rx) in SCP mode, a timeslot select input
pin (S1) in GCI slave mode, and a mode select pin (M1) in GCI master mode.
SCPCLK/S2/M2
This pin has three functions. It is the clock input pin (SCPCLK) in SCP mode, a timeslot select input
pin (S2) in GCI slave mode, and a mode select pin (M2) in GCI master mode.
SCPEN/GCIEN
This pin has two functions. It is the SCP enable input pin (SCPEN) in SCP mode, and the GCI enable
input pin (GCIEN) in GCI mode. Refer to the section on GCI for details on how the device enters
GCI mode.
TSEN/FST/BCL/LBA
This pin is initially high impedance, but can be programmed to have three separate functions. When
the TSEN signal is enabled via the SCP, this pin becomes an open drain output that pulls low when
data is being output from D out . This signal can then be used to enable an external driver in applications
where the IDL2 2B+D data goes off–board (PBXs, etc.).
Freescale Semiconductor, Inc.
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MC145574
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