MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 104

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MC145574AAER2

Manufacturer Part Number
MC145574AAER2
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145574AAER2

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
12–2
12.4
MULTIFRAME INTERRUPTS IN AN NT-CONFIGURED MC145574
The NT will generate an interrupt either once every multiframe, or only in the event of a new Q channel
nibble having been received. A new Q channel nibble is defined as one which differs from the previous
Q nibble.
Table 12–2 illustrates how to configure an NT for either of these options.
Interrupt Every
Frame No.
Multiframe
BR3(2)
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
1
2
X
Freescale Semiconductor, Inc.
0
1
For More Information On This Product,
Table 12–1. S Channel Data Transmission
Fa Bit Position
Go to: www.freescale.com
NT to TE
Table 12–2. Multiframe Interrupts
Enable Multiframing
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
MC145574
Interrupt
NR4(2)
0
1
1
NT to TE
M Bit
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Multiframing never causes an interrupt
An interrupt is generated on the reception of a
new Q Channel nibble
An interrupt is generated every multiframe
NT to TE
SC1.1
SC2.1
SC3.1
SC4.1
SC5.1
SC1.2
SC2.2
SC3.2
SC4.2
SC5.2
SC1.3
SC2.3
SC3.3
SC4.3
SC5.3
SC1.4
SC2.4
SC3.4
SC4.4
SC5.4
SC1.1
SC2.1
S Bit
MC145574
IRQ
Fa Bit Position
TE to NT
Q1
Q2
Q3
Q4
Q1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MOTOROLA

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