MC145574AAER2 Freescale Semiconductor, MC145574AAER2 Datasheet - Page 24

• Manufacturer Part Number: MC145574AAER2
• Manufacturer: Freescale Semiconductor

Specifications of MC145574AAER2

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3–2
3.7.1
3.7.2
3.5
3.6
3.7
3.8
3.9
ACTIVATION OF S/T LOOP BY TE
The TE activates an inactive loop by transmitting INFO 1 to the NT. This is accomplished in the
MC145574 by setting NR2(3) to a 1. Note that this bit is internally reset to 0 after the internal activation
state machine has recognized its active transition.
The NT, upon detecting INFO 1 from the TE, responds with INFO 2. The TE, upon receiving a signal
from the NT, ceases transmission of INFO 1, reverting to transmitting INFO 0. After synchronizing
to the received signal and having fully verified that it is INFO 2, the TE responds with INFO 3, thus
activating the loop.
ACTIVATION PROCEDURES IGNORED
The MC145574 has the capability of being forced into the highest transmission state. This is accom-
plished by setting BR7(7) to a 1. Thus when this bit is set in the NT, it forces the NT to transmit INFO 4.
Correspondingly, in the TE, setting this bit to 1 forces the TE to transmit INFO 3.
Note that CCITT I.430, ETSI ETS 300012, and ANSI T1.605 specifications allow a TE to be activated
by reception of INFO 4, without having to go through the intermediate handshaking. This is to allow
for the situation where a TE is connected to an already active loop.
However, an NT can not be activated by a TE sending it INFO 3, without going through the intermediate
INFO 1, INFO 2, INFO 3, and INFO 4 states.
This “Activation Procedures Ignored” feature is provided for test purposes, allowing the NT to forcibly
activate the TE(s). In the TE, the forced transmission of INFO 3 enables verification of the TEs opera-
tion.
FRAME SYNC
NT Mode
When the S/T transceiver in the NT mode is receiving INFO 3 from the TE(s) and has achieved frame
synchronization, it sets the FSYNC status bit NR1(0) high.
TE Mode
When the TE is receiving either INFO 2 or INFO 4 from the NT, and has achieved frame synchronization,
the MC145574 internally sets the SCP nibble bit, NR1(0). NR1(0) performs this function in both the
NT and TE modes, for the MC145574.
ACTIVATION INDICATION
NR1(3), the activation indication bit, is used to signify that the loop is fully active. When the MC145574
is configured as an NT, this corresponds to the NT transmitting INFO 4 and receiving INFO 3. When
the MC145574 is configured as a TE, this corresponds to it transmitting INFO 3 and receiving INFO 4.
When the loop is in the fully active state, NR1(3) is internally set high.
NR1(2)
NR1(2) is set by the MC145574 S/T transceiver to indicate an error condition has been detected by
the activation state machine of the transceiver, as outlined in CCITT I.430, ETSI ETS 300012, and
ANSI T1.605. The low–to–high level transition of the EI bit corresponds to the EI1 error indication
reporting, while the high–to–low level transition of the EI bit corresponds to the EI2 error indication
reporting recovery. Note that NR1(2) is a read only bit.
ERROR INDICATION (EI)
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MC145574
MOTOROLA